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Liz Cray
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Old Pages/Electronics/FPGAExercise3.md
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Old Pages/Electronics/FPGAExercise3.md
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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Digital Design and FPPGA Workshop
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HacDC
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William Gibb (teachmeFPGA@gmail.com)
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Week 3 - Introduction to Combinatorial Verilog
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Full adder and ALU exercise
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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For our exercises this week, we'll be working with a few different modeling
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styles, focused around a 4-bit full adder. We'll be working with a model
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where the 1 bit full adder circuit is explicitly defined, and break that down
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into half adders, behavioral and structural models.
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The full adder circuit can be constructed from 1-bit half adder circuits.
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The truth table for the half adder is as follows.
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A B | S Cout
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=========
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0 0 | 0 0
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0 1 | 1 0
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1 0 | 1 0
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1 1 | 0 1
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=========
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S = A xor B
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Cout = A and B
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Two of these cells, plus an additional OR gate, can be used to implement a
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full adder. The S output of the first half adder cell is connected to the
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input of the second cell, as is the Cin. The S output of the second cell is
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the sum S. The Cout is computed by ORing the Cout of both cells.
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Likewise, the truth table for the Full Adder is as follows, for reference.
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Cin A B | S Cout
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===============
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0 0 0 | 0 0
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0 0 1 | 1 0
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0 1 0 | 1 0
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0 1 1 | 0 1
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1 0 0 | 1 0
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1 0 1 | 0 1
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1 1 0 | 0 1
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1 1 1 | 1 1
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================
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To do
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0) Copy the full adder codes below to files in your working directory.
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Be sure to copy a makefile to the directory.
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0.a) mkdir a new directory for this example. name it something useful, such as "adder_exercise"
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0.b) create a new file for each verilog module, in the form modulename.v where module name is the name of the module. We'll need full_adder.v, full_adder_4bit.v, add test_adder.v.
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0.c) copy and paste the code for each module into the file. be sure that anything in the file that isn't verilog code is commented out.
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0.d) if your in the vm, type copymake.sh into the command line to copy a makefile into your working directory
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1) Change the values of the makefile to test the full adder.
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1.a) Change the line SRC and TESTBENCH to include only the .v files created earlier. if you need to add a new source to a project, add it to your makefile as well.
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2) Verify the full adder works by simulation.
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3) Write a description of the half adder, at gate level
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4) Write a full adder description, using the half adders you wrote in step
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3. Give this full adder module a different module name than the provided
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model.
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5) Write a 4 bit full adder module using the new 1 bit full adder. Be sure to
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give it a module name different than the name of the provided module.
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6) Take a break if you feel needed...or keep on coding
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7) Write a 4 bit full adder module using the new 1 bit full adder from step 6.
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Be sure to give it a module name different than the name of the provided
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module.
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8) One last adder - Write a 4 bit behavioral adder module. Use 4 bit inputs
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and outputs in this module. Again, give it a new name.
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9) Add the new models to the makefile.
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-half adder
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-full adder from half adders
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-4 bit full adder from step 5
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-full adder from step 6
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-4 bit full adder from step 7
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-4 bit full adder from step 8
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9) Modify the testbench to instantiate the new modules. You'll need to
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instantiate the 4 bit full adder from step 5, step 7 and step 8. This is why
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they all need to have unique module names. You'll need to add three 4 bit
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wires for connecting the sum output of these new adders, as well as
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three 1 bit wires for connecting the cout output of these new adders.
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10) Simulate and verify all of the models behave the same way.
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Once this is done, and you have simulated the adders and shown that they all
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behave the same way, you'll have built the following types of modules
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- Structural Model (step 5)
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- Behavioral & Hierarchical Model (step 7)
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- Behavioral Model (step 8)
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After that is done, people are encouraged to take the ALU presented in the
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slides and are encouraged to expand the functionality of the ALU to 8 total
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functions. The functions that should be added to the ALU are as follows:
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- r = ~A (R equals the complement of A)
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- r = A ^ B (R equals A xor B)
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- r = A << B (R equals A left shifted B bits)
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After this functionality has been added to the ALU model, the test bench used
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for the 4 bit full adder can be modified to simulate the ALU.
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Steps to do this
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0) Copy the test bench and makefile to your working directory
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1) Add/remove wires and regs as needed
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2) Replace the DUT with the ALU
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3) Expand the inputs in order to test all of the ALU functions.
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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Full Adder Code
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module full_adder(a, b, cin, sum, cout);
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input a, b, cin;
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output sum, cout;
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reg sum, cout;
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always @(a or b or cin)
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begin
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sum = a ^ b ^ cin;
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cout= (a & b) | (a & cin) | (b & cin);
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end
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endmodule
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module full_adder_4bit (a, b, cin, sum, cout);
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input[3:0] a, b;
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input cin;
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output [3:0] sum;
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output cout;
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wire c1, c2, c3;
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// instantiate 1-bit adders
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full_adder FA0(a[0],b[0], cin, sum[0], c1);
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full_adder FA1(a[1],b[1], c1, sum[1], c2);
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full_adder FA2(a[2],b[2], c2, sum[2], c3);
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full_adder FA3(a[3],b[3], c3, sum[3], cout);
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endmodule
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module test_adder;
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reg[3:0] a, b;
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reg cin;
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wire [3:0] sum;
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wire cout;
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full_adder_4bit dut(a, b, cin,
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sum, cout);
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initial
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begin
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a = 4'b0000;
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b = 4'b0000;
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cin= 1'b0;
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#50;
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a = 4'b0101;
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b = 4'b1010;
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// sum = 1111, cout= 0
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#50;
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a = 4'b1111;
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b = 4'b0001;
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// sum = 0000, cout= 1
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#50;a = 4'b0000;
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b = 4'b1111;
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cin= 1'b1;
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// sum = 0000, cout= 1
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#50;
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a = 4'b0110;
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b = 4'b0001;
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// sum = 1000, cout= 0
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end // initial begin
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initial
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begin
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$dumpfile ("waves.lxt");
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$dumpvars(0,test_adder);
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end
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endmodule// test_adder
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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ALU Code
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module mul16(i0,i1,prod);
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input [15:0] i0,i1;
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output [31:0] prod;
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// this is a magnitude multiplier
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// signed arithmetic later
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assign prod = i0 * i1;
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endmodule
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module add32(i0,i1,sum);
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input [31:0] i0,i1;
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output [31:0] sum;
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assign sum = i0 + i1;
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endmodule
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module sub32(i0,i1,diff);
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input [31:0] i0,i1;
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output [31:0] diff;
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assign diff = i0 - i1;
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endmodule
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module mux32two(i0,i1,sel,out);
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input [31:0] i0,i1;
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input sel;
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output [31:0] out;
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assign out = sel? i1 : i0;
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endmodule
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module mux32three(i0,i1,i2,sel,out);
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input [31:0] i0,i1,i2;
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input [1:0] sel;
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output [31:0] out;
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reg[31:0] out;
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always @ (i0 or i1 or i2 or sel)
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begin
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case (sel)
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2???b00: out = i0;
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2???b01: out = i1;
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2???b10: out = i2;
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default: out = 32???bx;
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endcase
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end
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endmodule
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module alu(a, b, f, r);
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input [31:0] a, b;
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input [2:0] f;
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output [31:0] r;
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// wire declarations
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wire [31:0] addmux_out, submux_out;
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wire [31:0] add_out, sub_out, mul_out;
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// module declarations
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mux32two adder_mux(b, 32'd1, f[0], addmux_out);
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mux32two sub_mux(b, 32'd1, f[0], submux_out);
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add32 our_adder(a, addmux_out, add_out);
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sub32 our_subtracter(a, submux_out, sub_out);
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mul16 our_multiplier(a[15:0], b[15:0], mul_out);
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mux32three output_mux(add_out, sub_out, mul_out, f[2:1], r);
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endmodule
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[Category:FPGAWorkshop](Category:FPGAWorkshop "wikilink")
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