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FL-501 CSS for both clock domains (#264)

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* CSS for both clock domains. Stale LSE detection and RTC domain reset on start.
* migrate to f4

Co-authored-by: aanper <mail@s3f.ru>
This commit is contained in:
あく
2020-12-11 15:34:17 +03:00
committed by GitHub
parent df27d775bf
commit 46537f4470
15 changed files with 114 additions and 7 deletions
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firmware/targets/f3/f3.ioc
+5 -1
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@@ -43,6 +43,7 @@ PCC.Ble.PowerLevel=Min
COMP1.Mode=COMP_POWERMODE_MEDIUMSPEED
PB6.Signal=USART1_TX
PB6.Mode=Asynchronous
NVIC.TAMP_STAMP_LSECSS_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
SPI1.CalculateBaudRate=4.0 MBits/s
PC3.Signal=GPIO_Analog
PD0.Signal=GPIO_Output
@@ -71,6 +72,7 @@ ProjectManager.BackupPrevious=false
VP_SYS_VS_tim17.Signal=SYS_VS_tim17
PC4.GPIO_Label=CC1101_G0
FREERTOS.HEAP_NUMBER=4
RCC.LSE_Drive_Capability=RCC_LSEDRIVE_MEDIUMLOW
PB1.GPIO_Label=BUTTON_DOWN
NVIC.TIM2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true
SPI1.DataSize=SPI_DATASIZE_8BIT
@@ -124,6 +126,7 @@ I2C1.CustomTiming=Disabled
PA4.GPIO_Label=PA4
ProjectManager.CustomerFirmwarePackage=
PC4.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
NVIC.RCC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:false
RCC.HSI48_VALUE=48000000
PC2.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
PA6.GPIOParameters=GPIO_Label
@@ -402,6 +405,7 @@ Mcu.IP14=SPI1
PB4.Mode=Full_Duplex_Master
Mcu.IP13=RTC
Mcu.IP16=SYS
RCC.LSE_Timout=1000
Mcu.IP15=SPI2
PC14-OSC32_IN.Mode=LSE-External-Oscillator
RCC.VCOInputFreq_Value=16000000
@@ -537,7 +541,7 @@ OSC_OUT.Locked=true
PA4.GPIOParameters=GPIO_Label
PC2.GPIO_PuPd=GPIO_PULLUP
PB15.GPIOParameters=GPIO_Label
RCC.IPParameters=ADCFreq_Value,AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EnableCSSLSE,EnbaleCSS,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSIOscState,PLLM,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGCLockSelection,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSCLockSelectionVirtual,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
RCC.IPParameters=ADCFreq_Value,AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,EnableCSSLSE,EnbaleCSS,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_Drive_Capability,LSE_Timout,LSI_VALUE,MCO1PinFreq_Value,MSIOscState,PLLM,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RFWKPClockSelection,RFWKPFreq_Value,RNGCLockSelection,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSCLockSelectionVirtual,SMPSFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
ProjectManager.AskForMigrate=true
Mcu.Name=STM32WB55RGVx
NVIC.SavedPendsvIrqHandlerGenerated=false